University of California, Berkeley CS 61C61C HW5

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Q1 Single-Cycle Datapath 4 Points I think we've had enough of Datapath in Lecture and Discussion (or not), but here, have some more anyways! And no, this homework is not optional. We have reprodu... ced the RISC-V single-cycle pipeline here. Using the following delays for the rest of the problem. Assume any component not listed is negligible in calculations. ELEMENT REGISTER CLK-TO-Q REGISTER SETUP MUX ALU MEMREAD MEM WRITE REGFILE READ REGFILE Parameter Delay (ps) 30 20 25 200 250 200 150 20 Q1.1 Critical Path 1 Point What is the critical path delay of this circuit? Your answer should be in units of ps. The path starts at PC and ends at write data, since that's one register to register. Make sure you understand why this doesn't start from Regfile Read. [Show More]

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