EEE/CSC 120 HARDWARE LAB 2 ANSWER SHEET Chandler-Gilbert Community CollegeCSC 120Hardware Lab 2.ALL ANSWERS CORRECT

Document Content and Description Below

EEE/CSC 120 HARDWARE LAB 2 ANSWER SHEET Operation of Adder and Comparator Name: Sergio Jimenez_____________ Task 0-1: Building a HALF-ADDER Paste a copy of your half-adder timing diagram and your... Verilog here. Please keep in mind, your timing waveform should include all the input combinations of A,B (0,0); (0,1); (1,0) and (1,1). Task 0-2: Building the Three-Bit Full-Adder Paste a copy of your full-adder timing diagram and your Verilog here. Please keep in mind, your timing waveform should include all the input combinations of A,B,C (0,0,0); (0,0,1); (0,1,0); (0,1,1); (1,0,0); (1,0,1); (1,1,0) and (1,1,1). Full Adder Verilog 2 Full Adder timing diagram FULL ADDER Truth TABLE TIME ns A B C SUM CARRY (0-10) 0 0 0 0 0 (10-20) 0 0 1 1 0 (20-30) 0 1 0 1 0 (30-40) 0 1 1 0 1 (40-50) 1 0 0 1 0 (50-60) 1 0 1 0 1 (60-70) 1 1 0 0 1 70-80 1 1 1 1 1 Please comment on any issues that you may have encountered. There were no issues in this part of the lab. 3 [Show More]

Last updated: 1 year ago

Preview 1 out of 8 pages