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# University of Florida - CDA 3101 Practice Final Exam Solution Latest Update

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University of Florida - CDA 3101 Practice Final Exam Solution (Latest 2020 / 2021) 1 CDA 3101 Final Exam (Sample) Last Name ____________________ Time: 2 hrs. First Name ____________________ Hono... r Code Statement On my honor, I have neither given nor received unauthorized aid on this exam. _______________________ ________________________ Signature UFID Show all your work to get partial/full credit. You can use a calculator. 1. (10 points) Write (in binary) the IEEE 754 single-precision representation of the number 18.2510. 2. (15 points) Consider two different implementations, I1 and I2, of the same instruction set. There are three classes of instructions (A, B, and C) in the instruction set. I1 has a clock rate of 6 GHz, and I2 has a clock rate of 4 GHz. The average number of cycles for each instruction class on I1 and I2 is given in the following table. Class CPI on I1 CPI on I2 C1 Usage C2 Usage A 2 1 40% 50% B 3 2 20% 25% C 5 2 40% 25% The table also contains a summary of average proportion of instruction classes generated by two different compilers (C1, and C2). Assume each compiler uses the same number of instructions for a given program but that the instruction mix is as described in the table. 3. (15 points) Implement the recursive function sillymultiply() given below in the MIPS assembly language. You may assume that the result always fits the 32-bit resgisters. int sillymultiply(int x, int y) 4 4. (20 points) Imagine I want to support the bge \$t0, \$t1, label, which compares \$t0 and \$t1 and branches only if \$t0 >= \$t1 (without breaking the rest of the instructions like add, sub, and, or, beq, lw, sw etc.). The instruction uses I-format representation (6 bits opcode, 5 bit rs, 5 bit rt, 16 bits label). Assume that the ALU generates another output ‘sign’ which is 1 when the ALU output is negative. (Hint: \$t0 >= \$t1 if \$t0 - \$t1 >= 0). a. Make changes to the single-cycle datapath and control shown below to support this instruction. b. Complete the table given below by writing the values (0/1/X) next to each control signal to show the values that would exist in the circuit after all the “work” for executing this instruction has completed, right before the moment that the rising edge of the next clock cycle occurs. 5. (20 points) Look at the following code. The pipelined datapath is given on the last page for your reference. addi \$t0, \$t0, 4 lw \$v0, 0(\$t0) data hazard on \$t0 sw \$v0, 20(\$t1) data hazard on \$v0 lw \$s0, 60(\$t0) add \$s1, \$s0, \$s0 data hazard on \$s0 sub \$s1, \$s1, \$s0 data hazard on \$s1 sub \$s4, \$s1, \$s5 data hazard on \$s1 a. Determine where the hazards occur and on which register and write it against each instruction above. See above b. Indicate in the chart below what stage each instruction is in at what cycle, where forwarding occurs (draw an arrow from where the value is produced to where the value is used), and where stalls or flushes occur. In the chart below, you may have more/less spaces than you need. Make sure you fill in the instructions in the first column as they would execute. c. Which two registers of the register file are being read in cycle 8? d. How many cycles does it take to execute the above code completely? e. Can you reorder the code to reduce the number of cycles it takes to execute this code, without changing the code result? If yes, show how. 6. (5 points) Describe (not just give the name) two schemes that can be used to resolve branch hazards. The pipelined datapath is given on the last page for your reference. See slides/book 7. (5 points) The forwarding unit in the pipelined system discussed in class checks the following 4 conditions to identify cases when forwarding will be necessary. Condition1: If EX/Mem.RegisterRD = ID/EX.RegisterRS Condition2: If EX/Mem.RegisterRD = ID/EX.RegisterRT Condition3: If Mem/WB.RegisterRD = ID/EX.RegisterRS Condition4: If Mem/WB.RegisterRD = ID/EX.RegisterRT Consider the following code and identify which condition(s) are true for the forwarding required between the instruction pairs (sub, and) and (sub, or). sub \$2, \$1, \$3 and \$12, \$2, \$5 or \$13, \$6, \$2 (sub, and): Condition 1 (sub, or) : Condition 4 https://www.coursehero.com/file/5877096/CDA3101PracticeFinalExamSoln/ This study resource was shared via CourseHero.com 8 [Show More]

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